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SPC564L54L5 Datasheet(PDF) 113 Page - STMicroelectronics |
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SPC564L54L5 Datasheet(HTML) 113 Page - STMicroelectronics |
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113 / 160 page  SPC56XL60/54 Electrical characteristics Doc ID 15457 Rev 8 113/160 3.13 FMPLL electrical characteristics Table 24. FMPLL electrical characteristics Symbol Parameter Conditions Min Typ Max Unit fREF_CRYSTAL fREF_EXT D FMPLL reference frequency range(1) Crystal reference 4 — 40 MHz fPLL_IN D Phase detector input frequency range (after pre- divider) —4 — 16 MHz fFMPLLOUT D Clock frequency range in normal mode — 4 — 120(2) MHz fFREE P Free running frequency Measured using clock division (typically ÷16) 20 — 150 MHz fsys D On-chip FMPLL frequency(2) —16 — 120 MHz tCYC D System clock period — — — 1 / fsys ns fLORL fLORH D Loss of reference frequency window(3) Lower limit 1.6 — 3.7 MHz Upper limit 24 — 56 fSCM D Self-clocked mode frequency(4),(5) —20 — 150 MHz tLOCK P Lock time Stable oscillator (fPLLIN = 4 MHz), stable VDD —— 200 µs tlpll D FMPLL lock time (6), (7) —— — 200 μs tdc D Duty cycle of reference —40 — 60 % CJITTER T CLKOUT period jitter(8),(9),(10),(11) Long-term jitter (avg. over 2 ms interval), fFMPLLOUT maximum –6 — 6 ns Δt PKJIT T Single period jitter (peak to peak) PHI @ 120 MHz, Input clock @ 4 MHz —— 175 ps PHI @ 100 MHz, Input clock @ 4 MHz —— 185 ps PHI @ 80 MHz, Input clock @ 4 MHz —— 200 ps Δt LTJIT T Long term jitter PHI @ 16 MHz, Input clock @ 4 MHz —— ±6 ns fLCK D Frequency LOCK range — –6 — 6 % fFMPLLOUT fUL D Frequency un-LOCK range — –18 — 18 % fFMPLLOUT fCS fDS D Modulation depth Center spread ±0.25 — ±2.0 % fFMPLLOUT Down spread –0.5 — -8.0 fMOD D Modulation frequency(12) — — — 100 kHz 1. Considering operation with FMPLL not bypassed. 2. With FM; the value does not include a possible +2% modulation |
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