STW82102B datasheet(19/67 Pages) STMICROELECTRONICS

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STW82102B

Electrical characteristics

Doc ID 018516 Rev 2

19/67

Table 9.

Phase noise performance(1)

Parameters

Conditions

Min.

Typ.

Max.

Unit

In band phase noise floor, closed loop(2)

Normalized In Band Phase Noise

Floor (LO)

ICP=4 mA, PLL BW = 50 kHz

(including reference clock

contribution)

--230

dBc/Hz

In Band Phase Noise Floor (LO)

-230+20log(N)+10log(FPFD) dBc/Hz

PLL integrated phase noise

Integrated Phase Noise

(single sided)

100 Hz to 40 MHz

FLO=2.050 GHz, FSTEP=200 kHz,

ICP=3 mA, PLL BW = 25 kHz

--45.3

dBc

0.44

° rms

LOA (1500 MHz to 1800 MHz) – open loop

Phase Noise @ 1 kHz

-69

dBc/Hz

Phase Noise @ 10 kHz

-96

dBc/Hz

Phase Noise @ 100 kHz

-118

dBc/Hz

Phase Noise @ 1 MHz

-139

dBc/Hz

Phase Noise @ 10 MHz

-153

dBc/Hz

Phase Noise Floor @ 40 MHz

-156

dBc/Hz

LOB (1900 MHz to 2200 MHz) – open loop

Phase Noise @ 1 kHz

-64

dBc/Hz

Phase Noise @ 10 kHz

-91

dBc/Hz

Phase Noise @ 100 kHz

-115

dBc/Hz

Phase Noise @ 1 MHz

-136

dBc/Hz

Phase Noise @ 10 MHz

-152

dBc/Hz

Phase Noise Floor @ 40 MHz

-156

dBc/Hz

Phase Noise SSB. VCO amplitude set to maximum value [11]. All the closed-loop performances are specified using a

Reference Clock signal at 76.8 MHz with phase noise of -144 dBc/Hz @1 kHz offset, -157 dBc/Hz @10 kHz offset and

-168 dBc/Hz of noise floor.

Normalized PN = Measured LO PN – 20log(N) – 10log(FPFD) where N is the VCO divider ratio (N=B*P+A) and FPFD is the

comparison frequency at the PFD input

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