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THC63LVDR84B Datasheet(PDF) 5 Page - THine Electronics, Inc.

Part # THC63LVDR84B
Description  LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER (Rising Edge Clock)
PDF  10 Pages
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Manufacturer  THINE [THine Electronics, Inc.]
Direct Link  http://www.thine.co.jp/index_e.html
Logo THINE - THine Electronics, Inc.

THC63LVDR84B Datasheet(HTML) 5 Page - THine Electronics, Inc.

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Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.
THC63LVDR84B_Rev.2.2_E
Switching Characteristics
Vcc = VCC = PVCC = LVCC
Symbol
Parameter
Min.
Typ.
Max.
Units
tRCP
CLK OUT Period
VCC = 2.5 - 2.7V
14.28
T
50.0
ns
VCC = 2.7 - 3.0V
14.28
T
66.6
ns
VCC = 3.0 - 3.6V
11.76
T
66.6
ns
tRCH
CLK OUT High Time
3T/7
ns
tRCL
CLK OUT Low Time
4T/7
ns
tRCD
RCLK +/- to CLK OUT Delay
5T/7
ns
tRS
TTL Data Setup to CLK OUT
0.35T-0.3
ns
tRH
TTL Data Hold from CKL OUT
0.45T-1.6
ns
tTLH
TTL Low to High Transition Time
2.0
3.0
ns
tTHL
TTL High to Low Transition Time
1.8
3.0
ns
tRIP1
Input Data Position0 (T = 11.76ns)
-0.4
0.0
0.4
ns
tRIP0
Input Data Position1 (T = 11.76ns)
T/7-0.4
T/7
T/7+0.4
ns
tRIP6
Input Data Position2 (T = 11.76ns)
2T/7-0.4
2T/7
2T/7+0.4
ns
tRIP5
Input Data Position3 (T = 11.76ns)
3T/7-0.4
3T/7
3T/7+0.4
ns
tRIP4
Input Data Position4 (T = 11.76ns)
4T/7-0.4
4T/7
4T/7+0.4
ns
tRIP3
Input Data Position5 (T = 11.76ns)
5T/7-0.4
5T/7
5T/7+0.4
ns
tRIP2
Input Data Position6 (T = 11.76ns)
6T/7-0.4
6T/7
6T/7+0.4
ns
tRPLL
Phase Lock Loop Set
10.0
ms
AC Timing Diagrams
TTL Output
8pF
20%
80%
20%
80%
tTLH
tTHL
TTL Output
TTL Output Load



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