AD2S80ATD datasheet(3/16 Pages) AD

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AD2S80A

Parameter

Conditions

Min

Typ

Max

Units

DATA LOAD

Sense

Internally Pulled High (100 k

Ω)

150

300

to +VS. Logic LO Allows

Data to be Loaded into the

Counters from the Data Lines

BUSY

Sense

Logic HI When Position O/P

Changing

Width

200

600

Load

Use Additional Pull-Up

LSTTL

DIRECTION

Sense

Logic HI Counting Up

Logic LO Counting Down

Max Load

LSTTL

RIPPLE CLOCK

Sense

Logic HI

All 1s to All 0s

All 0s to All 1s

Width

Dependent on Input Velocity

300

Reset

Before Next Busy

Load

LSTTL

DIGITAL INPUTS

High Voltage, VIH

INHIBIT, ENABLE

2.0

DB1–DB16, Byte Select

±V

S = ± 10.8 V, VL = 5.0 V

Low Voltage, VIL

INHIBIT, ENABLE

0.8

DB1–DB16, Byte Select

±V

S = ± 13.2 V, VL = 5.0 V

DIGITAL INPUTS

High Current, IIH

INHIBIT, ENABLE

±100

µA

DB1–DB16

±V

S = ± 13.2 V , VL = 5.5 V

Low Current, IIL

INHIBIT, ENABLE

±100

µA

DB1–DB16, Byte Select

±V

S = ± 13.2 V, VL = 5.5 V

DIGITAL INPUTS

Low Voltage, VIL

ENABLE = HI

1.0

SC1, SC2, Data Load

±V

S = ± 12.0 V, VL = 5.0 V

Low Current, IIL

ENABLE = HI

–400

µA

SC1, SC2, Data Load

±V

S = ± 12.0 V, VL = 5.0 V

DIGITAL OUTPUTS

High Voltage, VOH

DB1–DB16

2.4

RIPPLE CLK, DIR

±V

S = ± 12.0 V, VL = 4.5 V

IOH = 100 µA

Low Voltage, VOL

DB1–DB16

0.4

RIPPLE CLK, DIR

±V

S = ± 12.0 V, VL = 5.5 V

IOL = 1.2 mA

THREE-STATE LEAKAGE

DB1–DB16 Only

Current IL

±V

S = ± 12.0 V, VL = 5.5 V

±100

µA

VOL = 0 V

±V

S = ± 12.0 V, VL = 5.5 V

±100

µA

VOH = 5.0 V

NOTES

1Refer to small signal bandwidth.

2Output offset dependent on value for R6.

3Refer to timing diagram.

Specifications subject to change without notice.

All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.

AD2S80A

REV. A

–3–

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