AD8522 datasheet(2/8 Pages) AD

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AD8522–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Condition

Min

Typ

Max

Units

STATIC PERFORMANCE

Resolution

Bits

Relative Accuracy

INL

-1.5

±0.5

+1.5

LSB

Differential Nonlinearity

DNL

Monotonic

-1

±0.5

LSB

Zero-Scale Error

VZSE

Data = 000H

+0.5

Full-Scale Voltage

VFS

Data = FFFH

4.079

4.095

4.111

Volts

Full-Scale Tempco2, 3

TCVFS

±15

ppm/

°C

MATCHING PERFORMANCE

Linearity Matching Error

∆V

FSA/B

±1

LSB

ANALOG OUTPUT

Output Current

IOUT

Data = 800H,

∆V

OUT

≤ 3 LSB

±5mA

Load Regulation at Half-Scale

LDREG

RL = 402

Ω to ∞, Data = 800

LSB

Capacitive Load

No Oscillation

500

REFERENCE OUTPUT

Output Voltage

VREF

2.484

2.500

2.516

Output Source Current4

IREF

∆V

REF < 18 mV

Line Rejection

LNREJ

0.025

0.08

%/V

Load Regulation

LDREG

IREF = 0 to 5 mA, Data = 800H

0.025

0.1

%/mA

LOGIC INPUTS & OUTPUTS

Logic Input Low Voltage

VIL

0.8

Logic Input High Voltage

VIH

2.4

Input Leakage Current

IIL

µA

Input Capacitance

CIL

Logic Output Voltage Low

VOL

IOL = 1.6 mA

0.4

Logic Output Voltage High

VOH

IOH = 400

µA

3.5

TIMING SPECIFICATIONS

3, 5

Clock Width High

tCH

Clock Width Low

tCL

Load Pulse Width

tLDW

Data Setup

tDS

Data Hold

tDH

Clear Pulse Width

tCLRW

Load Setup

tLD1

Load Hold

tLD2

Select

tCSS

Deselect

tCSH

Clock to SDO Propagation Delay

tPD

AC CHARACTERISTICS

3, 5

Voltage Output Settling Time

±1 LSB of Final Value

µs

Crosstalk

Signal Measured at DAC Output,

While Changing Opposite LDA/B

DAC Glitch

Half-Scale Transition

nV s

Digital Feedthrough

DFT

Signal Measured at DAC Output,

While Changing Data Without LDA/B

nV s

SUPPLY CHARACTERISTICS

Positive Supply Current

IDD

VDD = 5.5 V, VIH = 2.4 V or VIL = 0.8 V

VDD = 5 V, VIL = 0 V

Power Dissipation

PDISS

VDD = 5 V, VIH = 2.4 V or VIL = 0.8 V

VDD = 5 V, VIL = 0 V

Power Supply Sensitivity

PSS

∆V

DD =

±5%

0.002

0.004

%/%

NOTES

11 LSB = 1 mV for 0 V to +4.095 V output range.

2Includes internal voltage reference error.

3These parameters are guaranteed by design and not subject to production testing.

4Very little sink current is available at the V

REF pin. Use external buffer if setting up a virtual ground.

5All input control signals are specified with t

r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.

7Power Dissipation is calculated I

DD × 5 V.

Specifications subject to change without notice.

(@ VDD = +5.0 V

10%, RL = No Load, –40 C

≤ T

≤ +85 C, both DACs tested, unless

otherwise noted)

REV. A

–2–

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