AD9830AST datasheet(2/16 Pages) AD

2 / 16 page

REV. A

–2–

AD9830–SPECIFICATIONS1

Parameter

AD9830A

Units

Test Conditions/Comments

SIGNAL DAC SPECIFICATIONS

Resolution

Bits

Update Rate (fMAX)

MSPS max

IOUT Full Scale

mA max

Output Compliance

V max

DC Accuracy

Integral Nonlinearity

±1

LSB typ

Differential Nonlinearity

±0.5

LSB typ

DDS SPECIFICATIONS

Dynamic Specifications

Signal-to-Noise Ratio

dB min

fMCLK = fMAX , fOUT = 2 MHz

Total Harmonic Distortion

–53

dBc max

fMCLK = fMAX , fOUT = 2 MHz

Spurious Free Dynamic Range (SFDR)

fMCLK = 6.25 MHz, fOUT = 2.11 MHz

Narrow Band

(

±50 kHz)

–72

dBc min

(

±200 kHz)

–68

dBc min

Wide Band (

±2 MHz)

–50

dBc min

Clock Feedthrough

–55

dBc typ

Wake Up Time

ms typ

Power-Down Option

Yes

VOLTAGE REFERENCE

Internal Reference @ +25

°C

1.21

Volts typ

TMIN to TMAX

1.21

± 7%

Volts min/max

REFIN Input Impedance

Ω typ

Reference TC

100

ppm/

°C typ

REFOUT Impedance

300

Ω typ

LOGIC INPUTS

VINH, Input High Voltage

VDD–0.9

V min

VINL, Input Low Voltage

0.9

V max

IINH, Input Current

µA max

CIN, Input Capacitance

pF max

POWER SUPPLIES

fOUT = 2 MHz

AVDD

4.75/5.25

V min/V max

DVDD

4.75/5.25

V min/V max

IAA

mA max

IDD

6 + 0.5/MHz

mA typ

IAA + IDD

mA max

Low Power Sleep Mode

0.25

mA typ

1 M

Ω Resistor Tied Between

mA max

REFOUT and AGND

(VDD = +5 V

5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT;

RSET = 1 k ; RLOAD = 51

for IOUT and IOUT unless otherwise noted)

NOTES

1Operating temperature range is as follows: A Version: –40

°C to +85°C.

2All dynamic specifications are measured using IOUT. 100% production tested.

MCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz.

4Measured with the digital inputs static and equal to 0 V or DVDD.

5The Low Power Sleep Mode current is 2 mA typically when a 1 M

Ω resistor is

not tied from REFOUT to AGND.

The AD9830 is tested with a capacitive load of 50 pF. The part can be operated

with higher capacitive loads, but the magnitude of the analog output will be attenu-

ated. For example, a 10 MHz output signal will be attenuated by 3 dB when the

load capacitance equals 250 pF.

Specifications subject to change without notice.

FULL-SCALE

CONTROL

10-BIT

DAC

SIN

ROM

ON-BOARD

REFERENCE

REFOUT

REFIN

ADJUST

COMP

IOUT

Ω

50pF

Ω

50pF

AVDD

RSET

Ω

10nF

Figure 1. Test Circuit with Which Specifications Are

Tested

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