AD9873 datasheet(32/39 Pages) AD

32 / 39 page

REV. 0

AD9873

–32–

MQFP

TOP VIEW

(Pins Down)

AGND IQ

I IN+

I IN–

AGND IQ

REFT8

REFB8

AGND IQ

AVDD IQ

DRVDD

REF CLK

DRGND

DGND SD

SDELTA0

SDELTA1

DVDD SD

CA_ENABLE

CA DATA

CA CLK

DVDD OSC

OSCIN

XTAL

DGND OSC

AGND PLL

PLL FILTER

AVDD PLL

DVDD PLL

DGND PLL

AVDD Tx

Tx+

Tx–

DRGND

DRVDD

(MSB) IF(11)

IF(10)

IF(9)

IF(8)

IF(7)

IF(6)

IF(5)

IF(4)

IF(3)

IF(2)

IF(1)

IF(0)

(MSB) Rx IQ(3)

Rx IQ(2)

Rx IQ(1)

Rx IQ(0)

Rx SYNC

DRGND

DRVDD

MLCK

DVDD

DGND

Tx SYNC

(MSB) Tx IQ(5)

Tx IQ(4)

Tx IQ(3)

Tx IQ(2)

AD9873

AVDD

0.1 F

10 F

0.01 F

0.1 F 0.01 F

0.01 F

0.1 F

10 F

0.01 F

10 F

0.1 F

10 F

0.1 F

0.1 F10 F0.1 F

0.1 F

EXTERNAL

POWER SUPPLY

DECOUPLING

DGND

Tx GND

OSC GND

AGND IQ

AGND

VAS

VDS

VDR

0.1 F

10 F

0.1 F

10 F

Figure 24. Power Supply Decoupling

POWER AND GROUNDING CONSIDERATIONS

In systems seeking to simultaneously achieve high speed and high

performance, the implementation and construction of the printed

circuit board design is often as important as the circuit design.

Proper RF techniques must be used in device selection, placement,

routing, supply bypassing, and grounding. Figure 24 illustrates

proper power supply decoupling. Split-ground technique can

be used to isolate digital and high-speed clock generation noise

from the analog front ends. The analog front end may be

further split to minimize crosstalk between the transmit and

receive sections. Noise-sensitive video-IF signals can also be

separated from the more robust IQ-ADC signal path. One com-

mon ground underneath the chip connects all ground splits and

assures short distances for ground pin connections. Figure 24

uses two separate power supplies. VAS powers the analog and

clock generation section of the chip while VDS is used for the

digital signals of the chip. An extra power supply VDR is only

needed in applications that require lower level digital outputs.

DRVDD and DVDD pins should be connected together for normal

mode. VDS (and VDR) should not be directly connected to the

power supply of noisy digital signal processing chips. It might

even be considered as an analog supply. Ferrite beads and 10 F

decoupling capacitors isolate power supplies between functional

blocks. Each supply pin is further decoupled with a 0.1 F multi-

layer ceramic capacitor that is mounted as close as possible to

the pin. In the high-speed PLL and DAC sections additional

0.01

F capacitors may be required as shown in Figure 24.

AD9873 Datasheet(PDF) 32 Page - Analog Devices

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