ADAS3023BCPZ datasheet(27/32 Pages) AD

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Data Sheet

ADAS3023

to access the data result prior to initiating a new conversion

produces an invalid result.

Upon the device returning from power-down mode or from a reset

when the default CFG is not used, there is no tACQ requirement

because the first two conversions from power-up are undefined/

invalid because the one-deep delay pipeline requirement must

be satisfied to reconfigure the device to the desired setting.

SERIAL DATA INTERFACE

The ADAS3023 uses a simple 4-wire interface and is compatible

with FPGAs, DSPs, and common serial interfaces such as a

serial peripheral interface (SPI), QSPI™, and MICROWIRE®. The

interface uses the CS, SCK, SDO, and DIN signals. Timing signals

for a serial interface are shown in Figure 47.

SDO is activated when CS is asserted. The conversion result is

output on SDO and updated on the SCK falling edges. Simulta-

neously, the 16-bit CFG word is updated, if needed, on the serial

data input (DIN). The state of BUSY/SDO2 (Bit 0) determines the

output format of the MSB data when SDO is activated after the

EOC. Note that, in Figure 47, SCK is shown as idling high. SCK

can idle high or low, requiring the system developer to design an

interface that suits setup and hold times for both SDO and DIN.

Figure 47. Serial Timing

DIN

(MOSI)

SDO

(MISO)

SCK

tDINH

tDINS

tSDOV

tSDOH

tSCKL

tSCK

tSCKH

tDIS

tEN

Rev. 0 | Page 27 of 32

ADAS3023BCPZ Datasheet(PDF) 27 Page - Analog Devices