SPC5604BF2MLL6 datasheet(81/109 Pages) FREESCALE

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tHI

SR D Data hold time for inputs

Master mode

—

Slave mode

——

tSUO7

CC D Data valid after SCK edge Master mode

—

Slave mode

—

160

tHO7

CC D Data hold time for outputs Master mode

—

Slave mode

—

1 Operating conditions: CL = 10 to 50 pF, SlewIN = 3.5 to 15 ns.

2 Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK

starts before CSn is asserted. DSPI2 has only SLOW SCK available.

3 Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is

deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.

4 The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay

between internal CS and internal SCK must be higher than

tCSC to ensure positive tCSCext.

5 The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between

internal CS and internal SCK must be higher than

tASC to ensure positive tASCext.

6 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of the DSPI_MCR.

7 SCK and SOUT configured as MEDIUM pad

Table 47. DSPI characteristics1 (continued)

No.

Symbol

Parameter

DSPI0/DSPI1

DSPI2

Unit

Min

Typ

Max

Min

Typ

Max

SPC5604BF2MLL6 Datasheet(PDF) 81 Page - Freescale Semiconductor, Inc

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