CDCU877AGQL datasheet(3/23 Pages) TI

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CDCU877,, CDCU877A

1.8-V PHASE LOCK LOOP CLOCK DRIVER

SCAS688D – JUNE 2005 – REVISED JULY 2007

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

GQL/ZQL

RHA/RTB

AGND

Analog ground

AVDD

Analog power

Clock input with a (10 k

Ω to 100 kΩ) pulldown resistor

Complementary clock input with a (10 k

Ω to 100 kΩ) pulldown

resistor

FBIN

Feedback clock input

FBIN

Complementary feedback clock input

FBOUT

Feedback clock output

FBOUT

Complementary feedback clock output

Output enable (asynchronous)

Output select (tied to GND or VDD)

B2, B3, B4, B5,

GND

C2, C5, H2, H5,

Ground

J2, J3, J4, J5

D2, D3, D4, E2,

1, 6, 9, 15, 20, 23,

VDDQ

E5, F2, G2, G3,

Logic and output power

28, 31, 36

G4, G5

A2, A1, D1, J1, K3,

3, 11, 14, 16, 19,

Y[0:9]

Clock outputs

A5, A6, D6, J6, K4

29, 33, 34, 38, 39

A3, B1, C1, K1,

2, 12, 13, 18, 17,

Y[0:9]

K2, A4, B6, C6,

Complementary clock outputs

30, 32, 35, 37, 40

K6, K5

FUNCTION TABLE

INPUTS

OUTPUTS

AVDD

FBOUT

PLL

GND

Bypassed/Off

GND

Bypassed/Off

GND

Bypassed/Off

GND

Bypassed/Off

Y7 Active

1.8 V Nominal

Y7 Active

1.8 V Nominal

Off

Reserved

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