OMAP3530ECBC72 datasheet(213/264 Pages) TI1

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OMAP3530/25 Applications Processor

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SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

Table 6-76. McSPI3 Interface Switching Requirements – Master Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SM1

tw(CLK)

Pulse duration, mcspix_clk high or low

0.45*P(5)

0.55*P(5)

0.45*P(5)

0.55*P(5)

SM4

td(CLKAE-SIMOV)

Delay time, mcspix_clk active edge to

–2.1

11.3

–5.3

23.6

mcspix_simo shifted

SM5

td(CSnA-CLKFE)

Delay time, mcspix_csi active Modes 1

–4.4 + A(6)

–10.1 + A(6)

to mcspix_clk first edge

and 3

Modes 0

–4.4 + B(7)

–10.1 + B(7)

and 2

SM6

td(CLK-CSn)

Delay time, mcspix_clk last

Modes 1

B – 4.4(7)

B – 10.1(7)

edge to mcspix_csi inactive

and 3

Modes 0

A(6) – 4.4

A(6) – 10.1

and 2

SM7

td(CSnAE-SIMOV)

Delay time, mcspix_csi active Modes 0

11.3

23.6

edge to mcspix_simo shifted

and 2

(5)

P = mcspi3_clk clock period

(6)

Case P = 20.8 ns, A = (TCS + 0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a bit

field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x Technical Reference Manual

(TRM) [literature number SPRUF98].

(7)

B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x

Technical Reference Manual (TRM) [literature number SPRUF98].

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