CY25561

Document Number: 38-07242 Rev. *F

Page 3 of 12

Pinout

Figure 1. Pin Configuration

XIN/CLK

SSCLK

XOUT

CY25561

1

2

3

4

8

7

6

5

VDD

VSS

S0

S1

SSCC

Pin Definitions

Pin

Name

Type

Description

I

Clock or crystal connection input. Refer to Table 1 for input frequency range selection.

P

Positive power supply

P

Power supply ground

4

SSCLK

O

Modulated clock output

5

SSCC

I

Spread spectrum clock control (enable/disable) function. SSCG function is enabled when

input is high and disabled when input is low. This pin is pulled high internally.

6

S1

I

Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth

selection and tri-level logic programming. See Figure 2. Pin 6 has internal resistor divider

7

S0

I

Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth

selection and tri-level logic programming. See Figure 2. Pin 7 has internal resistor divider

O

Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock

Table 1. Frequency and Spread Percentage Selection (Center Spread)

50–100 MHz (Low Range)

Input

Frequency

(MHz)

S1=M

S0=M

(%)

S1=M

S0=0

(%)

S1=1

S0=0

(%)

S1=0

S0=0

(%)

S1=0

S0=M

(%)

50–60

4.3

3.9

3.3

2.9

2.7

60–70

4.0

3.6

3.1

2.6

2.5

70–80

3.8

3.4

2.9

2.5

2.4

80–100

3.5

3.1

2.7

2.2

2.1

100–166 MHz (High Range)

Input

Frequency

(MHz)

S1=1

S0=M

(%)

S1=0

S0=1

(%)

S1=1

S0=1

(%)

S1=M

S0=1

(%)

100–120

3.0

2.4

1.5

1.3

120–130

2.7

2.1

1.4

1.1

130–140

2.6

2.0

1.3

1.1

140–150

2.6

2.0

1.3

1.1

150–166

2.5

1.8

1.2

1.0

Select the

Frequency and

Center Spread %

desired and then

set S1, S0 as

indicated.

Select the

Frequency and

Center Spread %

desired and then

set S1, S0 as

indicated.