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EVAL-AD1871EBZ Datasheet(PDF) 7 Page - Analog Devices

Part # EVAL-AD1871EBZ
Description  Stereo Audio, 24-Bit, 96 kHz, Multibit - ADC
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

EVAL-AD1871EBZ Datasheet(HTML) 7 Page - Analog Devices

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AD1871
DATA INTERFACE TIMING (CASCADE MODE–MASTER)
Mnemonic
Description
Min
Typ
Max
Unit
Comment
tBCHDC
BCLK High Delay
20
ns
From MCLK Rising
tBCLDC
BCLK Low Delay
20
ns
From MCLK Falling
tBLRDC
LRCLK Delay
10
ns
From BCLK Rising
tBDDC
DOUT Delay
10
ns
From BCLK Rising
tBDIS
DIN Setup
10
ns
To BCLK Rising
tBDIH
DIN Hold
10
ns
From BCLK Rising
LRCLK
MCLK
DOU T
BCLK
tBCHDC
tBCLDC
tBLRDC
tBDDC
Figure 4. Master Cascade Interface Timing
DATA INTERFACE TIMING (CASCADE MODE–SLAVE)
Mnemonic
Description
Min
Typ
Max
Unit
Comment
tBCHC
BCLK High Width
30
ns
tBCLC
BCLK Low Width
30
ns
tBDSDC
DOUT Delay
20
ns
From BCLK Rising
tLRSC
LRCLK Setup
10
ns
To BCLK Rising
tLRHC
LRCLK Hold
5
ns
From BCLK Rising
tBDIS
DIN Setup
10
ns
To BCLK Rising
tBDIH
DIN Hold
10
ns
From BCLK Rising
LRCLK
DOU T
BCLK
tLRSC
tBDSDC
tBCHC
tBCLC
tLRHC
Figure 5. Slave Cascade Interface Timing
DATA INTERFACE TIMING (MODULATOR MODE)
Mnemonic
Description
Min
Typ
Max
Unit
Comment
tMOCH
MODCLK High Width
MCLK
ns
tMOCL
MODCLK Low Width
MCLK
ns
tMHDD
MOD DATA High Delay
30
ns
From MCLK Rising
tMLDD
MOD DATA Low Delay
20
ns
From MCLK Falling
tMMDR
MODCLK Delay Rising
30
ns
MCLK Falling to MODCLK Rising
tMMDF
MODCLK Delay Falling
20
ns
MCLK Falling to MODCLK Falling
D[0 – 3 ]
MODCLK
tMHDD
tMOCH
tMOCL
tMLDD
Figure 6. Modulator Mode Timing



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