MT46V64M4 datasheet(21/91 Pages) MICRON

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN

256Mb: x4, x8, x16 DDR SDRAM

Electrical Specifications – DC and AC

Figure 2:

SSTL_2 Clock Input

Notes:

1. CK or CK# may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.

2. This provides a minimum of 1.15V to a maximum of 1.35V and is always half of VDDQ.

3. CK and CK# must cross in this region.

4. CK and CK# must meet at least VID(DC),min when static and is centered around VMP(DC).

5. CK and CK# must have a minimum 700mV peak-to-peak swing.

6. For AC operation, all DC clock requirements must also be satisfied.

7. Numbers in diagram reflect nominal values for all devices other than -5B.

Table 5:

Clock Input Operating Conditions

Notes: 1–5, 16, 17, and 31 apply to the entire table; Notes appear on page 35;

0°C

T

A  70°C; VDDQ = 2.5V ±0.2V, VDD = 2.5V ±0.2V (VDDQ = 2.6V ±0.1V, VDD = 2.6V ±0.1V for -5B)

Parameter/Condition

Symbol

Min

Max

Units

Notes

Clock input mid-point voltage: CK and CK#

VMP(DC)

1.15

1.35

7, 10

Clock input voltage level: CK and CK#

VIN(DC)

–0.3

VDDQ + 0.3

Clock input differential voltage: CK and CK#

VID(DC)

0.36

VDDQ + 0.6

7, 9

Clock input differential voltage: CK and CK#

VID(AC)

0.7

VDDQ + 0.6

Clock input crossing point voltage: CK and CK#

VIX(AC)

0.5 × VDDQ - 0.2

0.5 × VDDQ + 0.2

CK#

2.80V

Maximum clock level1

Minimum clock level1

–0.30V

1.25V

1.45V

1.05V

ID(AC)

VID(DC)

VMP(DC)

VIX(AC)

MT46V64M4 Datasheet(PDF) 21 Page - Micron Technology

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