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PD70F3559 Datasheet(PDF) 40 Page - Renesas Technology Corp |
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PD70F3559 Datasheet(HTML) 40 Page - Renesas Technology Corp |
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40 / 85 page  40 R01DS0142ED0100 Data Sheet Chapter 7 Peripherals specification 7.6 Timer timing Table 7-1 Timer timing Parameter Symbol Condition Ratings Unit Min Typ Max TAUAnI input High level width tTAIH n=0 a,b -- ns TAUAnI input Low level width tTAIL n=0 a,b -- ns TAUBnI input High level width tTBIH n=1 a,b a) With digital noise filter enabled: 2, 3, 4 or 5 x Tsamp + 20 (Tsamp shows sampling period specified in Noise filter macro. More than 1 PCLK width of Timer macro must be kept regarding DNF pass through pulse width. b) With digital noise filter disabled: 1xtSYNC+20 ( tSYNC: 1 PCLK of Timer macro) -- ns TAUBnI input Low level width tTBIL n=0 a,b -- ns TAUJnI input High level width tTJIH n=0,1 300 - - ns TAUJnI input High level width tTJIH 4.7 - - µs TAUJnI input High level width tTJIH b - - ns TAUJnI input Low level width tTJIL n=0,1 300 - - ns TAUJnI input Low level width tTJIL 4.7 - - µs TAUJnI input Low level width tTJIL b -- ns TAUAnO output cycle tTACYK n=0 - - 20 MHz TAUBnO output cycle tTBCYK n=1 - - 20 MHz TAUCnO output cycle tTCCYK n=2-7 - - 20 MHz TAUJnO output cycle tTJCYK n=0,1 - - 20 MHz TAPAnESO input High level width tWESH n=0 300 - - ns TAPAnESO input Low level width tWESL n=0 300 - - ns ENCAnTmIN high level width tWENmH n=0, m=A,B,Z a,b -- ns ENCAnTmIN low level width tWENmL n=0, m=A,B,Z a,b -- ns ENCAnTINm high level width tWENmH n=0, m=0-1 a,b -- ns ENCAnTINm low level width tWENmL n=0, m=0-1 a,b -- ns |
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