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ADRF6702ACPZ-R7 Datasheet(PDF) 26 Page - Analog Devices

Part # ADRF6702ACPZ-R7
Description  1200 MHz to 2400 MHz Quadrature Modulator
PDF  36 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADRF6702ACPZ-R7 Datasheet(HTML) 26 Page - Analog Devices

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ADRF6702
Data Sheet
Rev. B | Page 26 of 36
REGISTER 5—LO PATH AND MODULATOR
CONTROL (DEFAULT: 0
x0000D5)
With Register 5, Bits[2:0] set to 101, the LO path and modulator
control register is programmed as shown in Figure 46.
The modulator output or the complete modulator can be
disabled using the modulator bias enable and modulator
output enable addresses of Register 5.
The LO port (LOP and LON pins) can be used to apply an
external 2× LO (that is, bypass internal PLL) to the IQ
modulator. A differential LO drive of 0 dBm is recommended.
The LO port can also be used as an output where a 2× LO or
1× LO can be brought out and used to drive another mixer.
The nominal output power provided at the LO port is 3 dBm.
The mode of operation of the LO port is determined by the
status of the LOSEL pin (3.3 V logic) along with the settings
in a number of internal registers (see Table 10).
Table 10. LO Port Configuration1, 2
LON/LOP
Function
LOSEL
Register 5,
Bit DB5
(LDIV)
Register 5,
Bit DB4
(LXL)
Register 5,
Bit DB3
(LDRV)
Input (2× LO)
0
X
1
0
Output (Disabled)
0
X
0
0
Output (1× LO)
0
0
0
1
Output (1× LO)
1
0
0
0
Output (1× LO)
1
0
0
1
Output (2× LO)
0
1
0
1
Output (2× LO)
1
1
0
0
Output (2× LO)
1
1
0
1
1 X = don’t care.
2 LOSEL should not be left floating.
The internal VCO of the device can also be bypassed. In this
case, the charge pump output drives an external VCO through
the loop filter. The loop is completed by routing the VCO into
the device through the LO port.
RESERVED
MOD
BIAS
ENABLE
RF
OUTPUT
ENABLE
LO
OUTPUT
DIVIDER
LO
IN/OUT
CONTROL
LO
OUTPUT
DRIVER
ENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
MBE
DB6
DB5
DB4
DB3
DB2 DB1 DB0
0
0
0
0
RFEN
LDIV
LXL
LDRV
C3(1) C2(0) C1(1)
LDRV
0
1
LDIV
0
1
DIVIDE BY 1
DIVIDE BY 2 (DEFAULT)
LO OUTPUT DRIVER
ENABLE
DRIVER OFF (DEFAULT)
DRIVER ON
RFEN
0
1
DISABLE
ENABLE (DEFAULT)
RF OUTPUT ENABLE
LO OUTPUT DIVIDE MODE
CONTROL BITS
LXL
0
1
LO OUTPUT (DEFAULT)
LO INPUT
LO INPUT/OUTPUT CONTROL
MBE
0
1
DISABLE
ENABLE (DEFAULT)
MOD BIAS ENABLE
0
0
000
000
000
0
Figure 46. Register 5—LO Path and Modulator Control Register Map



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