ADRF6750ACPZ-R7 datasheet(39/40 Pages) AD

39 / 40 page

ADRF6750

Rev. A | Page 39 of

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

PIN 1

INDICATOR

TOP

VIEW

7.75

BSC SQ

8.00

BSC SQ

4.95

4.80 SQ

4.65

0.50

0.40

0.30

0.23

0.18

0.50 BSC

0.20 REF

12° MAX

0.80 MAX

0.65 TYP

1.00

0.85

0.80

6.50

REF

SEATING

PLANE

0.60 MAX

PIN 1

INDICATOR

COPLANARITY

0.08

0.05 MAX

0.02 NOM

0.30 MIN

EXPOSED

PAD

(BOTTOM VIEW)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 78. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

8 mm × 8 mm Body, Very Thin Quad

(CP-56-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model1

Temperature Range

Package Description

Package Option

ADRF6750ACPZ-R7

−40°C to

+85°C

56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel

CP-56-3

ADRF6750-EVALZ

Evaluation Board

1 Z = RoHS Compliant Part.

ADRF6750ACPZ-R7 Datasheet(PDF) 39 Page - Analog Devices

ADRF6750ACPZ-R7 Datasheet(HTML) 39 Page - Analog Devices

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