DM163006 datasheet(39/320 Pages) MICROCHIP

39 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 39

PIC18C601/801

4.0

MEMORY ORGANIZATION

There are two memory blocks in PIC18C601/801

devices. These memory blocks are:

• Program Memory

• Data Memory

Each block has its own bus so that concurrent access

can occur.

4.1

Program Memory Organization

PIC18C601/801 devices have a 21-bit program

counter that is capable of addressing up to 2 Mbyte of

external program memory space. The PIC18C601 has

an external program memory address space of 256

Kbytes. Any program fetch or TBLRD from a program

location greater than 256K will return all NOPs. The

PIC18C801 has an external program memory address

space of 2Mbytes. Refer to Section 5.0 (“External

Memory Interface”) for additional details.

The RESET vector address is mapped to 000000h and

the interrupt vector addresses are at 000008h and

000018h. PIC18C601/801 devices have a 31-level stack

to store the program counter values during subroutine

calls and interrupts. Figure 4-1 shows the program

memory map and stack for PIC18C601. Figure 4-2

shows the program memory map and stack for the

PIC18C801.

4.1.1

“BOOT RAM” PROGRAM MEMORY

PIC18C601/801 devices have a provision for configur-

ing the last 512 bytes of general purpose user RAM as

program memory, called “Boot RAM”. This is achieved

by configuring the PGRM bit in the MEMCON register

to ‘1’. (Refer to Section 5.0, “External Memory Inter-

face” for more information.) When the PGRM bit is ‘1’,

the RAM located in data memory locations 400h

through 5FFh (bank 4 through 5) is mapped to program

memory locations 1FFE00h to 1FFFFFh.

When configured as program memory, the Boot RAM is

to be used as a temporary “boot loader” for program-

ming purposes. It can only be used for program execu-

tion. A read from locations 400h to 5FFh in data

memory returns all ‘0’s. Any attempt to write this RAM

as data memory when PGRM = 1, does not modify any

of these locations. TBLWT instructions to these loca-

tions will cause writes to occur on the external memory

bus. The boot RAM program memory cannot be modi-

fied using TBLWT instruction. TBLRD instructions from

boot RAM will read memory located on the external

memory bus, not from the on-board RAM. Constants

that are stored in boot RAM are retrieved using the

RETLW

instruction.

The default RESET state (power-up) for the PGRM bit

is ‘0’, which configures 1.5K of data RAM and all pro-

gram memory as external. The PGRM bit can be set

and cleared in the software.

When execution takes place from “Boot RAM”, the

external system bus and all of its control signals will be

deactivated. If execution takes place from outside of

“Boot RAM”, the external system bus and all of its con-

trol signals are activated again.

Figure 4-3 and Figure 4-4 show the program memory

map and stack for PIC18C601 and PIC18C801, when

the PGRM bit is set.

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