Data Sheet

AD9361

Rev. D | Page 7 of 36

Parameter1

Symbol

Min

Typ

Max

Unit

Test Conditions/

Comments

DIGITAL DATA TIMING (CMOS),

VDD_INTERFACE = 2.5 V

DATA_CLK Clock Period

16.276

ns

61.44 MHz

DATA_CLK and FB_CLK Pulse

Width

ns

TX Data

TX_FRAME, P0_D, and

P1_D

Setup to FB_CLK

1

ns

Hold to FB_CLK

0

ns

DATA_CLK to Data Bus Output

Delay

0

1.2

ns

DATA_CLK to RX_FRAME Delay

0

1.0

ns

Pulse Width

ENABLE

ns

TXNRX

ns

FDD independent ENSM

mode

TXNRX Setup to ENABLE

0

ns

TDD ENSM mode

Bus Turnaround Time

Before RX

ns

TDD mode

After RX

ns

TDD mode

Capacitive Load

3

pF

Capacitive Input

3

pF

DIGITAL DATA TIMING (LVDS)

DATA_CLK Clock Period

4.069

ns

245.76 MHz

DATA_CLK and FB_CLK Pulse

Width

ns

TX Data

TX_FRAME and TX_D

Setup to FB_CLK

1

ns

Hold to FB_CLK

0

ns

DATA_CLK to Data Bus Output

Delay

0.25

1.25

ns

DATA_CLK to RX_FRAME Delay

0.25

1.25

ns

Pulse Width

ENABLE

ns

TXNRX

ns

FDD independent ENSM

mode

TXNRX Setup to ENABLE

0

ns

TDD ENSM mode

Bus Turnaround Time

Before RX

ns

After RX

ns

Capacitive Load

3

pF

Capacitive Input

3

pF

SUPPLY CHARACTERISTICS

1.3 V Main Supply Voltage

1.267

1.3

1.33

V

VDD_INTERFACE Supply

Nominal Settings

CMOS

1.2

2.5

V

LVDS

1.8

2.5

V

VDD_INTERFACE Tolerance

−5

+5

%

Tolerance is applicable

to any voltage setting

VDD_GPO Supply Nominal

Setting

1.3

3.3

V

When unused, must be

set to 1.3 V

VDD_GPO Tolerance

−5

+5

%

Tolerance is applicable

to any voltage setting

Current Consumption

VDDx, Sleep Mode

180

μA

Sum of all input currents

VDD_GPO

50

μA

No load

1

When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin

names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.