34

Am29DL800B

P R E L I M I NARY

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

Valid Data

(first read)

(second read)

(stops toggling)

DQ6/DQ2

Valid Data

Valid

Status

Valid

Status

Valid

Status

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle

21519A-25

Figure 21.

Toggle Bit Timings (During Embedded Algorithms)

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

21519A-26

Figure 22.

DQ2 vs. DQ6

Enter

Erase

Erase

Erase

Enter Erase

Suspend Program

Erase Suspend

Read

Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Suspend

Program

Resume

Embedded

Erasing