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AM79C970AVCW Datasheet(PDF) 64 Page - Advanced Micro Devices |
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AM79C970AVCW Datasheet(HTML) 64 Page - Advanced Micro Devices |
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64 / 219 page ![]() AMD P R E L I M I N A R Y 64 Am79C970A The following figure shows the beginning of a FIFO DMA write with the beginning of the buffer not aligned to a DWord boundary. The PCnet-PCI II controller starts off by writing only three bytes during the first data phase. This operation aligns the address for all other data trans- fers to a 32-bit boundary so that the PCnet-PCI II con- troller can continue bursting full DWords. 19436A-33 FRAME CLK AD IRDY TRDY C/ BE DEVSEL REQ GNT 1 23456 0000 0111 PAR PAR PAR DEVSEL is sampled 0001 PAR DATA DATA DATA ADD Figure 30. FIFO Burst Write At Start Of Unaligned Buffer |
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