AM79C985JC datasheet(18/48 Pages) AMD

18 / 48 page

Am79C985

PRELIMINARY

Notes:

1. CRS = Carrier Sense, COL = Collision, JAB = Jabber, LINK = Link, LB = Loop Back, PAR = Partition, DIS = Port Disabled,

blk = Blink (Number = period of Blink).

2. For the LDC0-2 setting of 000: If the port is partitioned, the LINK LED is off.

3. All LEDs blink 16 times at 260 ms per blink after reset.

4. All LEDs are on for approximately 4 seconds after reset.

5. LDC0-2 = ‘010’ and ‘011’ are undeﬁned.

The LEDs can also be controlled via the management

port. The Enable Software Override commands turn

the LEDs on regardless of the attributes selected for

display through the LDC setting. Enable Software

Override of Bank A LEDs causes the LDA0-4 and LDGA

pins to be driven LOW, and Enable Software Override

of Bank B LEDs causes the LDB0-4 and LDGB pins to

be driven LOW. The blink rate is set by the Software

Override LED Blink Rate command. The periods are

off, 512 ms, 1560 ms, or solid on.

LED software override is executed in two stages, by

ﬁrst issuing the blink rate (Software Override of LED

Blink Rate) and then issuing the command to enable

the particular port LEDs (Enable Software Override of

Bank

A/B LEDs). All port combinations selected for

software override control will reference the blink rate

last issued by the Software Override of the LED Blink

Rate command.

LDA0-4, LDB0-4, LDGA, and LDGB are open drain out-

put drivers that sink 12 mA of current to turn on the

LEDs. In a multiple eIMR+ conﬁguration, the outputs

from the global LED drivers (LDGA and LDGB) of each

chip can be tied together to drive a single pair of global

status LEDs.

CRS and COL are extended to make it easier for visual

recognition; that is, they will remain active for some

time even if the corresponding condition has expired.

Once carrier sense is active, CRS will remain active for

a minimum of 4 ms. Once a collision is detected, COL

is active for at least 4 ms. The exception to this rule is

for selection LDC0-2 = 111. For this selection, COL is

stretched to 100

µs.

When LDC0-2 = 000 or LDC0-2 = 001, the loopback at-

tribute (LB) for the AUI port is displayed on LDA0. LB is

true when DO on the MAU is successfully looped back

to DI on the AUI port. LB is false (off) if a loopback error

is detected, or if the AUI port is disabled or in the re-

verse mode. Transmit carrier sense is sampled at the

end of packet to determine the state of LB. The state of

LB remains latched until carrier sense is sampled again

for the next packet. The default/power-up state for LB is

false (off).

Figure 1 shows the recommended connection of LEDs.

When LDA0-4, LDB0-4, LDGA, or LDGB are LOW, the

LED lights.

Figure 1. Visual Monitoring Application—Direct

LED Drive

Table 2. LED Attribute-Monitoring Program Options

LED Control

Global LEDs

TP LEDs

AUI LEDs

LDC2

LDC1

LDC0

LDGA

LDGB

LDA1-4

LDB1-4

LDA0

LDB0

CRS

COL

LINK (Note 2)

PAR

CRS

COL

LINK

CRS

Reserved (Note 5)

CRS 260-ms blk

COL 260-ms blk

LINK

CRS 260-ms blk

PAR

COL 260-ms blk

CRS 260-ms blk

PAR

COL 260-ms blk

COL

JAB

LINK (Note 3)

CRS 512-ms blk

PAR (Note 3)

(Note 3)

CRS 512-ms blk

PAR (Note 3)

CRS

COL

LINK

CRS 130-ms blk

PAR or DIS

CRS 130-ms blk

PAR or DIS

CRS

COL

LINK (Note 4)

PAR 1.56-s blk

COL (Note 4)

(Note 4)

PAR 1.56-s blk

PAR (Note 4)

eIMR+

LED

Interface

LDA[4:0]

LDB[4:0]

LDGA

LDGB

VDD

Typical

20651A-6

20651B-6

AM79C985JC Datasheet(PDF) 18 Page - Advanced Micro Devices

AM79C985JC Datasheet(HTML) 18 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL