W25X05CLZPIG datasheet(16/51 Pages) WINBOND

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W25X05CL/10CL/20CL

Publication Release Date: March 23, 2012

- 16 -

Revision B

8.2.5 Write Disable (04h)

The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register

to a 0. The Write Disable instruction is entered by driving /CS

low, shifting the instruction code “04h”

into the DIO pin and then driving /CS high. WEL bit is automatically reset after Power-up and upon

completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase

instructions. Write Disable instruction can also be used to invalidate the Write Enable for Volatile

Status Register instruction

Figure 6. Write Disable Instruction Sequence Diagram

8.2.6 Read Status Register (05h)

The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is

entered by driving /CS

low and shifting the instruction code “05h” into the DIO pin on the rising edge of

CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most

significant bit (MSB) first as shown in figure 6. The Status Register bits are shown in figure 3 and

include the BUSY, WEL, BP1, BP0, TB and SRP bits (see description of the Status Register earlier in

this datasheet).

The Status Register instruction may be used at any time, even while a Program, Erase or Write Status

cycle is complete and if the device can accept another instruction. The Status Register can be read

continuously, as shown in Figure 7. The instruction is completed by driving /CS high.

Figure 7. Read Status Register Instruction Sequence Diagram

/CS

CLK

(IO

Mode 0

Mode 3

Mode 0

Mode 3

Instruction (04h)

High Impedance

W25X05CLZPIG Datasheet(PDF) 16 Page - Winbond