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LP621024DM-55LL Datasheet(PDF) 5 Page - AMIC Technology

Part # LP621024DM-55LL
Description  128K X 8 BIT CMOS SRAM
PDF  16 Pages
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

LP621024DM-55LL Datasheet(HTML) 5 Page - AMIC Technology

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LP621024D Series
(August, 2001, Version 1.0)
5
AMIC Technology, Inc.
AC Characteristics (TA = 0
°C to + 70°C, VCC = 5V ± 10%)
Symbol
Parameter
LP621024D-55LL
LP621024D-70LL
Unit
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55
-
70
-
ns
tAA
Address Access Time
-
55
-
70
ns
tACE1
Chip Enable Access Time
CE1
-
55
-
70
ns
tACE2
CE2
-
55
-
70
ns
tOE
Output Enable to Output Valid
-
30
-
35
ns
tCLZ1
Chip Enable to Output in Low Z
CE1
10
-
10
-
ns
tCLZ2
CE2
10
-
10
-
ns
tOLZ
Output Enable to Output in Low Z
5
-
5
-
ns
tCHZ1
Chip Disable to Output in High Z
CE1
0
20
0
25
ns
tCHZ2
CE2
0
20
0
25
ns
tOHZ
Output Disable to Output in High Z
0
20
0
25
ns
tOH
Output Hold from Address Change
5
-
5
-
ns
Write Cycle
tWC
Write Cycle Time
55
-
70
-
ns
tCW
Chip Enable to End of Write
50
-
60
-
ns
tAS
Address Setup Time
0
-
0
-
ns
tAW
Address Valid to End of Write
50
-
60
-
ns
tWP
Write Pulse Width
40
-
50
-
ns
tWR
Write Recovery Time
0
-
0
-
ns
tWHZ
Write to Output in High Z
0
25
0
30
ns
tDW
Data to Write Time Overlap
25
-
30
-
ns
tDH
Data Hold from Write Time
0
-
0
-
ns
tOW
Output Active from End of Write
5
-
5
-
ns
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.



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