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STM8S005C6T6 Datasheet(PDF) 85 Page - STMicroelectronics |
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STM8S005C6T6 Datasheet(HTML) 85 Page - STMicroelectronics |
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85 / 103 page ![]() Unit Fast mode I 2C(1) Standard mode I 2C Parameter Symbol Max (2) Min (2) Max (2) Min (2) μs 0.6 4.0 START condition hold time th(STA) μs 0.6 4.7 Repeated START condition setup time tsu(STA) μs 0.6 4.0 STOP condition setup time tsu(STO) μs 1.3 4.7 STOP to START condition time (bus free) tw(STO:STA) pF 400 400 Capacitive load for each bus line Cb (1) f MASTER, must be at least 8 MHz to achieve max fast I 2C speed (400kHz). (2) Data based on standard I2C protocol requirement, not tested in production. (3) The maximum hold time of the start condition has only to be met if the interface does not stretch the low time. (4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Figure 41: Typical application with I 2C bus and timing diagram (1) ai15385b S TART SDA I²C bus VDD VDD STM8Sx05xx SDA SCL tf(SDA) tr(SDA) SCL th(STA) tw(SCLH) tw(SCLL) tsu(SDA) tr(SCL) tf(SCL) th(SDA) S TART REPEATED S TART tsu(STA) tsu(STO) S TOP tsu(STA:STO) 1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD 85/103 DocID022186 Rev 3 Electrical characteristics STM8S005K6 STM8S005C6 |
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