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DSPIC33FJ64GP706 Datasheet(PDF) 24 Page - Microchip Technology |
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DSPIC33FJ64GP706 Datasheet(HTML) 24 Page - Microchip Technology |
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24 / 322 page  dsPIC33FJXXXGPX06/X08/X10 DS70286C-page 22 © 2009 Microchip Technology Inc. FIGURE 3-1: dsPIC33FJXXXGPX06/X08/X10 CPU CORE BLOCK DIAGRAM Instruction Decode and Control PCH PCL Program Counter 16-bit ALU 24 23 Instruction Reg PCU 16 x 16 W Register Array ROM Latch EA MUX Interrupt Controller Stack Control Logic Loop Control Logic Data Latch Address Latch Control Signals to Various Blocks 16 16 16 To Peripheral Modules Data Latch Address Latch 16 X RAM Y RAM Address Generator Units 16 Y Data Bus X Data Bus DMA Controller DMA RAM DSP Engine Divide Support 16 16 23 23 16 8 PSV and Table Data Access Control Block 16 16 16 16 Program Memory Data Latch Address Latch |
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