PCF8563 datasheet(24/50 Pages) NXP

24 / 50 page

PCF8563

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Product data sheet

Rev. 10 — 3 April 2012

24 of 50

NXP Semiconductors

PCF8563

Real-time clock/calendar

Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 14).

9.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 15).

9.3 System configuration

A device generating a message is a transmitter; a device receiving a message is a

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves (see Figure 16).

Fig 14. Bit transfer

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 15. Definition of START and STOP conditions

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

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