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L6924UTR Datasheet(PDF) 29 Page - STMicroelectronics |
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L6924UTR Datasheet(HTML) 29 Page - STMicroelectronics |
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29 / 37 page ![]() L6924U Additional applications information Doc ID 14716 Rev 2 29/37 9 Additional applications information 9.1 Selecting the input capacitor In most applications, a 1 µF ceramic capacitor, placed close to the VIN and VINSN pins can be used to filter the high frequency noise. 9.2 Selecting the output capacitor Typically, a 4.7 µF ceramic capacitor placed close to the VOUT and VOUTSN pin is enough to keep voltage control loop stable. This ensures proper operation of battery absent detection in removable battery pack applications. 9.3 Layout guidelines and demonstration board The thermal loop keeps the device at a constant temperature of approximately 120 °C which in turn, reduces ICHG. However, in order to maximize the current capability, it is important to ensure a good thermal path. Therefore, the exposed pad must be properly soldered to the board and connected to the other layer through thermal vias. The recommended copper thickness of the layers is 70 μm or more. The exposed pad must be electrically connected to GND. Figure 22 shows the thermal image of the board with the power dissipation of 1 W. In this instance, the temperature of the case is 89 °C, but the junction temperature of the device is given by the following equation: Equation 25 Where the RthJA of the device mounted on board is 75 °C/W, the power dissipated is 1 W, and the ambient temperature is 25 °C. In this case the junction temperature is: Equation 26 AMB DISS A THJ J T P R T + × = − C T J o 100 25 1 75 = + × = |
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