Device description and operation

L6747A

12/15

Doc ID 17126 Rev 1

Traces between the driver and the MOSFETS should be short and wide to minimize the

inductance of the trace, which in turn minimizes ringing in the driving signals. Moreover, the

VIA count should be minimized to reduce the related parasitic effect.

The use of a multi-layer printed circuit board is recommended.

Small signal components and connections to critical nodes of the application, as well as

bypass capacitors for the device supply, are also important. Place the bypass capacitor

(VCC, PVCC and BOOT capacitors) close to the device with the shortest possible loop,

using wide copper traces to minimize parasitic inductance.

Systems that do not use Schottky diodes in parallel with the low-side MOSFET might show

large negative spikes on the PHASE pin. This spike can be limited, as can the positive spike,

but has an additional consequence: it causes the bootstrap capacitor to be overcharged.

This extra charge can cause, in the worst case condition of maximum input voltage and

during particular transients, that boot-to-phase voltage exceeds the absolute maximum

ratings causing device failures. It is therefore suggested in this cases to limit this extra

also contributes in the limitation of the spike present on the BOOT pin.

For heat dissipation, place the copper area under the IC. This copper area may be

connected by internal copper layers through several VIAs to improve thermal conductivity.

The combination of copper pad, copper plane and VIAs under the driver allows the device to

achieve its best thermal performance.

Figure 7.

Driver turn-on and turn-off paths

Figure 8.

External component placement example

VCC

LS DRIVER

LS MOSFET

GND

LGATE

BOOT

HS DRIVER

HS MOSFET

PHASE

HGATE

VCC

Rboot

Cboot

1

2

3

4

LGATE

GND

PHASE

UGATE

VCC

EN

PWM

BOOT

5

6

7

8

C