UPSS1650

Preliminary

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

6 of 7

www.unisonic.com.tw

QW-R502-947.d



OPERATION DESCRIPTION(Cont.)

Iout

Vout

Large

Rcs

Small

Rcs

Figure 3. Adjustable output power by changing Rcs

Figure 4. Secondary current waveform

In CC operation, the CC loop control function of UTC UPSS1650 will keep a fixed proportion between secondary

inductance de-magnetization time (Tdemag) and switching cycle time (Tsw). The fixed proportion is

2

1

=

Tsw

Tdemag

(2)

Thus the output current is given by:

Ipk

×

N

N

×

4

1

=

Tsw

Tdemag

×

Ipk

×

N

N

×

2

1

=

Iout

S

P

S

P

(3)

Programmable Cable Drop Compensation

UTC UPSS1650 has a built-in cable voltage drop compensation to achieve good load regulation. An offset voltage

is generated at INV pin by an internal current flowing into the resistor divider. The current is inversely proportional to

the voltage of COMP pin. As a result, it is inversely proportional to the output load current. The voltage drop across

the cable is compensated by this offset voltage at INV pin. It can also be programmed by adjusting the resistance of

the divider to compensate the drop for various cable lines used.

Current Sensing and Leading Edge Blanking

Cycle-by-cycle current limiting is offered in UTC UPSS1650. The switch current is detected by a sense resistor

into the CS pin. When the power switch is turned on, a turn-on spike will occur on this resistor. A 500ns leading-edge

blanking is built in to avoid false-termination of the switching pulse so that the external RC filtering is no longer

needed.