MAS281 datasheet(9/55 Pages) DYNEX

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2.2.23 TRIGGER-GO CLOCK (TGCLK)

This clock input is used by the internal 16-bit trigger-go

counter. The trigger-go counter counts at the same frequency

as TGCLK.

2.2.24 TRIGGER-GO DISCRETE (TGO)

This active low output goes low whenever the trigger-go

counter overflows, i e., the counter rolls over to 0000. It returns

to the high state when the trigger-go counter is reset by

software via the GO XIO command.

2.2.25 DISABLE TIMER (DTIMER)

A low on this active low input disables timers A and B as

well as the trigger-go counter. A low also disables DMA access

by forcing DMAE low and DMAKN high. Raising DTIMERN

allows timers A and B and the trigger-go counter to resume

counting from the value at which they were stopped. A high

also allows normal DMA operation.

2.2.26 DISABLE TIMEOUT (DTO)

A low on this active low input will reset and disable the bus

fault timeout circuitry.

2.2.27 POWER DOWN INTERRUPT (PWRD)

A low on this active low input is captured in the Pl register

by a SYNCN high-to-low transition. This sets pending interrupt

0. This is the highest priority interrupt and cannot be masked or

disabled.

2.2.28 USER INTERRUPTS (INT02,08,10,11,13 AND 15)

A low on any of these active low inputs will be captured in

the Pl register by a SYNCN high-to-low transition and will set

pending interrupt levels 2, 8, 10, 11, 13, and 15, respectively.

Level 2 is the highest priority user level while level 15 is the

lowest priority. These interrupts are maskable and can be

disabled. Unused inputs should be pulled up to VDD.

[NOTE: The INTO2 service routine should clear the PI

2.2.29 I/0 DEDICATED INTERRUPTS (IOI1 & IOI2)

A low on either IOI1N or IOI2N will be captured in the Pl

interrupt levels 12 and 14, respectively. Unused inputs should

be pulled up to VDD.

[NOTE: Interrupt levels 1, 3, 4, 5, 6, 7, and 9 are dedicated

to internal machine interrupts.]

2.2.30 MEMORY PROTECT ERROR (MPROE)

A low on this active low input, captured by the SYNCN

high-to-low transition, is used to inform the module that an

access fault, execute protect, or write protect violation has

been detected. Bit O of the module Fault Register (FT) is set if

this signal goes low during a memory cycle; bit 1 is set if it goes

low during a DMA cycle. Either condition immediately sets

pending interrupt level 1 and in the case of a memory cycle

error, causes the currently executing MIL-STD-1750A

instruction to be aborted.

Although the MAS281 aborts the macroinstruction, system

memory management, and / or block protect hardware is

responsible for preventing the erroneous bus cycle from

accessing memory. To effectively use this feature, MPROEN

should be pulled low prior to the high-to-low SYNCN transition

of the next machine cycle. This can easily be accomplished by

injecting wait states to hold off the DSN rising edge (write

cycle) and the SYNCN falling edge (read cycle) until the

system protection circuitry can decide whether or not to allow

the transaction.

2.2.31 MEMORY PARITY ERROR (MPE)

A low on this active low input, captured by the SYNCN

high-to-low transition, is used to inform the module that a parity

error has been detected during a memory transfer. Bit 2 of the

module Fault Register (FT) is set when this signal goes low.

This, in turn, causes pending interrupt level 1 to be set.

2.2.32 PROGRAMMED I/O PARITY ERROR (PIOPE)

A low on this active low input, captured by the SYNCN

high-to-low transition, is used to inform the module that a parity

error has been detected during an external l/O transfer. Bit 3 of

the module Fault Register (FT) is set when this signal goes

low. This, in turn, causes pending interrupt level 1 to be set.

2.2.33 DMA PARITY ERROR (DMAPE)

A low on this active low input, captured by the SYNCN

high-to-low transition, is used to inform the module that a parity

error has been detected during a DMA data transfer. Bit 4 of

the module Fault Register (FT) is set when this signal goes low

This, in turn, causes pending interrupt level 1 to be set.

2.2.34 EXTERNAL ADDRESS ERROR (EXADE)

A low on this active low input, captured by the SYNCN

high-to-low transition, is used to inform the module that a

system address error has been detected. Bit 8 of the module

Fault Register (FT) is set when this signal goes low during a

Bit

Device

Console

MMU

BPU

Output Discrete Register

11-0

Unused

Table 1: Configuration Register Bit Assignment

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