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HM5259165B Datasheet(PDF) 22 Page - Elpida Memory |
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HM5259165B Datasheet(HTML) 22 Page - Elpida Memory |
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22 / 63 page  HM5259165B/HM5259805B/HM5259405B-75/A6 Data Sheet E0118H10 22 Operation of the SDRAM The following chapter shows operation example of the products below. Organization Input/output mask CAS latency 8-Mword × 16-bit × 4 bank DQMU/DQML 2/3 16-Mword × 8-bit × 4 bank DQM 32-Mword × 4-bit × 4 bank DQM Note: The SDRAM should be used according to the product capability (See “Features”, “Pin Description” and “AC Characteristics”). Read/Write Operations Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. An interval of t RCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the ( CAS Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation. The burst length can be set to 1, 2, 4, 8. The start address for a burst read is specified by the column address and the bank select address (BA0/BA1) at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the CAS Latency. The CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4, 8, the Dout buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output. The CAS latency and burst length must be specified at the mode register. |
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