UR5515-S08-R datasheet(5/8 Pages) ETL

5 / 8 page

UR5515

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

5 of 8

www.unisonic.com.tw

QW-R502-056,A

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TYPICAL APPLICATION CIRCUIT

R1= R2= 100KΩ

COUT(min)=10μF(Ceramic) + 1000μF under the worst case testing condition

CSS=1μF, CIN = 40μF(low ESR), CCNTL= 47μF

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APPLICATIONS INFORMATION

Please note the point of thermal shutdown will be degraded by around 20℃while VCNTL equal to 5V compared

with 3.3V. It is highly recommended that to use the 3.3V rail acted as the VCNTL in SOP-8 package. Nevertheless,

this small footprint of PCB for plastic SOP-8 package is not enough to dissipate effectively the heat generated

when operating at high current levels. In order to control die operating temperatures, the PCB layout should allow

for maximum possible copper area at the four VCNTL pins. Besides, an appropriate power plane heat sink must be

used to prevent overstepping maximum junction temperature. The recommended SMT is as below.

The PCB heat sink copper area should be

solder painted without masked. This

approaches a "best case " pad heat sink .

UTC UR5515

(SOP-8)

Use vias to conduct the heat into the

buried or backside of PCB layer.

UR5515-S08-R Datasheet(PDF) 5 Page - E-Tech Electronics LTD