ICS844008I-46 datasheet(10/15 Pages) IDT

10 / 15 page

IDT™ / ICS™ LVDS CLOCK GENERATOR

ICS844008AKI-46 REV. A MAY 19, 2008

ICS844008I-46

FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR

SCHEMATIC LAYOUT

Figure 6 shows an example of ICS844008I-46 application

schematic. In this example, the device is operated at

= V

DDO

= 3.3V. The 18pF parallel resonant 25MHz crystal

is used. The C1 = 27pF and C2 = 27pF are recommended

To Logic

Input

pins

10uF

nQ2

VDDO

Set Logic

Input to

'0'

To Logic

Input

pins

FREQ_SEL

Zo = 50 Ohm

nQ7

nQ0

27pF

RD2

nQ6

VDD= VDDO=3.3V

VDD

nQ1

100

25MHz

VDD

VDDO

GND

RU2

Not Install

VDDO

27pF

0.1uF

Set Logic

Input to

'1'

Zo = 50 Ohm

Logic Control Input Examples

0.01u

VDDA

nQ6

0.1uF

RD1

Not Install

RU1

0.1uF

Zo = 50 Ohm

0.1uF

VDD

nQ7

18pF

VDD

ICS844008I-46

nQ0

GND

nQ1

VDDO

nQ2

nQ6

VDDO

nQ7

GND

0.1uF

Alternate

LVDS

Termination

for frequency accuracy. For different board layout, the C1

and C2 may be slightly adjusted for optimizing frequency

accuracy. Two examples of LVDS for receiver without built-

in termination are shown in this schematic.

FIGURE 6. ICS844008I-46 SCHEMATIC LAYOUT

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