GMS87C1102 datasheet(39/80 Pages) HYNIX

39 / 80 page

HYUNDAI MicroElectronics

GMS87C1102 / GMS87C1202

Oct. 1999 ver 1.0

14. Basic Interval Timer

The GMS87C1202 has one 8-bit Basic Interval Timer that

is free-run, can not stop. Block diagram is shown in Figure

14-1 .The 8-bit Basic interval timer register (BITR) is in-

creased every internal count pulse which is divided by

prescaler. Since prescaler has divided ratio by 8 to 1024,

the count rate is 1/8 to 1/1024 of the oscillator frequency.

As the count overflows from FFH to 00H, this overflow

causes to generate the Basic interval timer interrupt. The

BITF is interrupt request flag of Basic interval timer.

When write "1" to bit BTCL of CKCTLR, BITR register is

cleared to "0" and restart to count-up. The bit BTCL be-

comes "0" after one machine cycle by hardware.

If the STOP instruction executed after writing "1" to bit

WAKEUP of CKCTLR, it goes into the wake-up timer

mode. In this mode, all of the block is halted except the os-

cillator, prescaler ( only fxin

÷2048 ) and Timer0.

If the STOP instruction executed after writing "1" to bit

RCWDT of CKCTLR, it goes into the internal RC oscillat-

ed watchdog timer mode. In this mode, all of the block is

halted except the internal RC oscillator, Basic Interval

Timer and Watchdog Timer. More detail informations are

explained in Power Saving Function. The bit WDTON de-

cides Watchdog Timer or the normal 7-bit timer

Note: All control bits of Basic interval timer are in CKCTLR

(address ECH). Address ECH is read as BITR, writ-

ten to CKCTLR. Therefore, the CKCTLR can not be

accessed by bit manipulation instruction.

Figure 14-1 Block Diagram of Basic Interval Timer

Figure 14-2 CKCTLR : Clock Control Register

÷ 8

÷ 16

÷ 128

÷ 256

÷ 512

÷ 1024

÷ 32

÷ 64

STOP

WAKEUP

MUX

fxin

BITR (8BIT)

BITIF

BTS[2:0]

RCWDT

Internal RC OSC

Basic Interval Timer

Interrupt

BTCL

Clear

To Watchdog Timer

Clock Control Register

CKCTLR

ADDRESS : ECH

RESET VALUE : -0010111

WAKEUP

RCWDT

WDTON

BTCL

BTS2

BTS1

BTS0

Basic Interval Timer Clock Selection

000 : fxin

÷ 8

001 : fxin

÷ 16

100 : fxin

÷ 128

101 : fxin

÷ 256

110 : fxin

÷ 512

111 : fxin

÷ 1024

010 : fxin

÷ 32

011 : fxin

÷ 64

Symbol

Function Description

WAKEUP

1: Enables Wake-up Timer

0: Disables Wake-up Timer

RCWDT

1: Enables Internal RC Watchdog Timer

0: Disables Internal RC Watchdog Time

WDTON

1: Enables Watchdog Timer

0: Operates as a 7-bit Timer

BTCL

1: BITR is cleared and BTCL becomes "0" automatically

after one machine cycle, and BITR continue to count-up

Bit Manipulation Not Available

GMS87C1102 Datasheet(PDF) 39 Page - Hynix Semiconductor

GMS87C1102 Datasheet(HTML) 39 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL