ICS1523MLF datasheet(19/21 Pages) ICST

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Video Clock Synthesizer with I2C Programmable Delay

MDS 1523 Y

Revision 110905

Integrated Circuit Systems

525 Race Street, San Jose, CA 95126

tel (408) 297-1201

www.icst.com

ICS1523

Note 1- VOL must not fall below the level given so that the correct value for IOUT can be maintained.

Note 2- Measured at 135MHz, 3.6 VDC, 0oC, 20 pF, with 75

Ω Termination

Note 3- Measured at 135MHz, 3.6 VDC, 0oC, 20 pF, Unterminated

Analog Input (HSYNC)

Input High Voltage

VIH

1.7

5.5

Input Low Voltage

VIL

VSS - 0.3

1.1

Digital Inputs (SDA, SCL, EXTFB, OSC, I2CADDR)

Input High Voltage

VIH

25.5

Input Low Voltage

VIL

VSS - 0.3

0.8

Input Hysteresis

0.2

0.6

POR Threshold

VSS

1.8

Voltage that resets

SDA Digital Output

SDA Output Low Voltage

VOL

0.4

IOUT = 3ma

SDA Output High Voltage

VOH

6.0

Determined by

external Rset

resistor

PECL Outputs (CLK+, CLK-, CLK/2+, CLK/2-)

Output High Voltage

VOH

-VDD

IOUT=0

Maximum Output Frequency

FP MAX

250

MHz

VDDD = 3.3 V

Output Low Voltage *

VOL

1.0

IOUT =

Programmed Value

Duty Cycle

PDC

Transition Time - Rise

TPR

-1.0

Transition Time - Fall

TPF

-1.2

SSTL_3 Outputs (CLK, CLK/2, FUNC, LOCK/REF)

Output Resistance

-80

Ω

1 V < VO < 2 V

Maximum Output Frequency

Fs MAX

150

MHz

VDDD = 3.3 V

Duty Cycle

SDC

Clock and FUNC

Transition Time - Rise

TCR

-1.6

Clock and FUNC

Transition Time - Fall

TCF

-1.0

LOCK/REF Transition Time -

Rise

TLR

-3.0

LOCK/REF Transition Time - Fall

TLF

-2.0

Parameter

Symbol

Min.

Max.

Units

Notes

ICS1523MLF Datasheet(PDF) 19 Page - Integrated Circuit Systems

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