ICS548-03

Low Skew Clock Inverter and Divider

MDS 548-03

3

Revision 042700

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com

ADVANCE INFORMATION

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

Supply Voltage, VDD

Referenced to GND

7

V

Inputs

Referenced to GND

-0.5

VDD+0.5

V

Clock Output

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)

DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)

Operating Voltage, VDD

3

5.5

V

Input High Voltage, VIH, ICLK only

ICLK (Pin 1)

(VDD/2)+1

VDD/2

V

Input Low Voltage, VIL, ICLK only

ICLK (Pin 1)

VDD/2

(VDD/2)-1

V

Input High Voltage, VIH

All other inputs

2

V

Input Low Voltage, VIL

All other inputs

0.8

V

Output High Voltage, VOH, CMOS level

IOH=-8mA

VDD-0.4

V

Output High Voltage, VOH

IOH=-12mA

2.4

V

Output Low Voltage, VOL

IOL=12mA

0.4

V

IDD Operating Supply Current, 100 MHz clock S3=S2=S0=0, S1=1

TBD

mA

Short Circuit Current

Each output

±50

mA

Input Capacitance, S3, S2, S1, S0 , and OE

All inputs

5

pF

AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)

AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)

Input Frequency, clock input, PLL on

10

120

MHz

Input Frequency, clock input, PLL off

0

160

MHz

Output Frequency (see table on page 2)

Mode dependent

0

120

MHz

Output Clock Rise Time

0.8 to 2.0V

1

ns

Output Clock Fall Time

2.0 to 0.8V

1

ns

Output Clock Duty Cycle

at VDD/2

45

49 to 51

55

%

Output Enable Time, OE high to output on

50

ns

Output Disable Time, OE low to tri-state

50

ns

Absolute Clock Period Jitter, PLL modes

Deviation from mean

TBD

ps

One Sigma Clock Period Jitter, PLL modes

TBD

ps

Output clock skew for CLK, CLK, or CLK/2

at VDD/2

500

ps

Electrical Specifications

Note 1: The phase relationship between input and output clocks can change at power up. Use the ICS570 or ICS527 Zero Delay

Buffers for a guaranteed phase relationship.

External Components/Application Information

The device requires a 0.01 µF decoupling capacitor between pins 3 and 5, as close to the pins as possible.

Connect pin 2 directly to pin 3, and pin 6 directly to pin 5. Series termination resistors of 33

Ω can be used

on all used clock outputs, also close to the device. Leave any unused clock outputs floating. There are no

pull-up resistors on the input pins, so they should be connected directly to VDD or ground.