7-1083

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD4094BMS

CMOS 8-Stage Shift-and-Store

Bus Register

Pinout

CD4094BMS

TOP VIEW

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

STROBE

DATA

CLOCK

Q1

Q2

Q3

VSS

Q4

VDD

Q5

Q6

Q7

Q8

Q’S

QS

OUTPUT ENABLE

8-STAGE

SHIFT

REGISTER

8-BIT

STORAGE

REGISTER

3-STATE

OUTPUTS

SERIAL

OUTPUTS

10

9

Q’S

QS

VDD = 16

VSS = 8

DATA

2

CLOCK

3

STROBE

1

OUTPUT

ENABLE

15

PARALLEL OUTPUTS Q1 - Q8

(TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY)

Features

• High Voltage Type (20V Rating)

• 3-State Parallel Outputs for Connection to Common

Bus

• Separate Serial Outputs Synchronous to Both Positive

and Negative Clock Edges for Cascading

• Medium Speed Operation - 5MHz at 10V (typ)

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• Serial-to-Parallel Data Conversion

• Remote Control Holding Register

• Dual-Rank Shift, Hold, and Bus Applications

Description

CD4094BMS is a 8-stage serial shift register having a storage

latch associated with each stage for strobing data from the serial

input to parallel buffered 3-state outputs. The parallel outputs

may be connected directly to common bus lines. Data is shifted

on positive clock transitions. The data in each shift register stage

is transferred to the storage register when the STROBE input is

high. Data in the storage register appears at the outputs when-

ever the OUTPUT-ENABLE signal is high.

Two serial outputs are available for cascading a number of

CD4094BMS devices. Data is available at the QS serial output

terminal on positive clock edges to allow for high-speed opera-

tion in cascaded systems in which the clock rise time is fast. The

same serial information, available at the Q’S terminal on the next

negative clock edge, provides a means for cascading

CD4094BMS devices when the clock rise time is slow.

The CD4094BMS is supplied in these 16 lead outline packages:

Braze Seal DIP

H4X

Frit Seal DIP

H1F

Ceramic Flatpack

H6W

December 1992

File Number

3194