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UPD16334 Datasheet(PDF) 8 Page - NEC |
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UPD16334 Datasheet(HTML) 8 Page - NEC |
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8 / 12 page ![]() 8 µµµµµPD16334 SWITCHING CHARACTERISTICS (TA = 25 °C, VDD1 = 5 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V, Logic CL = 15 pF, Driver CL = 50 pF, tr = tf = 6.0 ns) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transmission tPHL1 CLK ↓ → A/B 55 ns Delay time tPLH1 55 ns tPHL2 CLK ↑ (LE = H) → O1 to O96 180 ns tPLH2 180 ns tPHL3 BLK → O1 to O96 165 ns tPLH3 165 ns tPHL4 PC → O1 to O96 160 ns tPLH4 160 ns tPHZ OE → O1 to O96 300 ns tPZH RL = 10 k Ω 180 ns tPLZ 300 ns tPZL 180 ns Rise Time tTLH O1 to O96 150 ns tTLZ RL = 10 k Ω 3 µs tTZH O1 to O96 150 ns Fall Time tTHL O1 to O96 150 ns tTHZ RL = 10 k Ω 3 µs tTZL O1 to O96 150 ns Maximum Clock fmax. When data is read, duty 50 % 25 MHz Frequency cascade connection, Duty 50 % 15 MHz Input Capacitance CI 15 pF TIMING REQUIREMENT (TA = –40 to +85 °C, VDD1 = 4. 75 to 5. 25 V, VSS1,2 = 0 V, tr = tf = 6.0 ns) Parameter Symbol Conditions MIN. TYP. MAX. Unit Clock Pulse Width PWCLK 20 ns Latch Enable Pulse Width PWLE 30 ns Blank Pulse Width PWBLK 200 ns PC Pulse Width PWPC 200 ns OE Pulse Width PWOE RL = 10 k Ω 3.3 µs Data Setup Time tsetup 10 ns Data Hold Time thold 10 ns Latch Enable Time 1 tLE1 25 ns Latch Enable Time 2 tLE2 5ns Latch Enable Time 3 tLE3 25 ns Latch Enable Time 4 tLE4 5ns |
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