AN3001

Configuring the demonstration board

Doc ID 15911 Rev 1

5/12

3

Configuring the demonstration board

3.1

Serial data input configuration

The TS4657 receives serial digital audio data through a 3-wire interface. SDAT is the serial

audio data input. The data is entered MSB first and is a two’s complement. The data can be

FORMAT2 as detailed in Table 3.

The level on both of these pins should be fixed before waking-up the chip.

3.2

Sample rate capability

Three external clock signals are applied to the TS4657. The MCLK is the external master

clock applied by the audio data processor. The LRCLK is the channel frequency, also called

LEFT/RIGHT clock, at which the digital words for each channel are input to the device. The

LRCLK clock is the sample rate of the audio data. The ratio MCLK/LRCLK must be an

integer, as shown in Table 4.

The BCLK is the bit clock and represents the clock at which the audio data is serially shifted

into the audio port. BCLK is linked to LRCLK. The minimum required BCLK frequency is

twice the audio sample rate multiplied by the number of bits in each audio word. Refer to

Table 3 for the BCLK/LRCLK ratio. MCLK, LRCLK and BCLK must be synchronous clock

signals.

Table 3.

Digital audio data formats supported by the TS4657

FORMAT2

FORMAT1

Data Format

BCLK/LRCLK ratio

Min

Max

00

Right-justified, 16-bit data

Data valid on rising edge of BCLK

32

256

01

Right-justified, 24-bit data

Data valid on rising edge of BCLK

48

256

10

Left-Justified, 16-bit up to 24-bit data

Data valid on rising edge of BCLK

2 x number of bits of data

256

11

I²S, 16-bit up to 24-bit data

Data valid on rising edge of BCLK

2 x number of bits of data

256

Table 4.

Audio data sampling rates

LRCLK (kHz)

MCLK (MHz)

256x

32

8.192

44.1

11.2896

48

12.288