SPI module description

AN2159

4/23

Doc ID 11400 Rev 3

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SPI module description

The STPM01-10 SPI interface supports a simple serial protocol, which is implemented in

order to enable a communication between a host system (microcontroller or PC) and the

device.

With this interface it is possible to perform the following tasks:

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remote reset of the device,

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temporary programming of internal configuration/calibration data and system signals,

●

STPM01 only: permanent programming in OTP memory of internal

configuration/calibration data,

●

reading of internal data registers (shown in Figure 5).

Four pins of the device are dedicated to this purpose: SCS, SYN, SCL, and SDA.

SCS, SYN and SCL are all input pins while SDA can be input or output according if the SPI

is in write or read mode.

The internal register are not directly accessible, rather a 32 bit of transmission latches are

used to pre-load the data before being read or written to the internal registers.

The condition in which SCS, SYN and SCL inputs are set to high level determines the idle

state of the SPI interface and no data transfer occurs. Any SPI operation should start from

this idle state.

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SCS: enables SPI operation when low.

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SYN: when SCS is low the SYN pin status select if the SPI is in read (SYN=1) or write

mode (SYN=0). When SCS is high and SYN is also high the results of the input or

output data are transferred to the transmission latches.

●

SCL: is the clock pin of the SPI interface. This pin function is also controlled by the SCS

status. If SCS is low, SCL is the input of serial bit synchronization clock signal. When

SCS is high, SCL is also high determining the idle state of the SPI.

●

SDA: is the data pin. If SCS is low, the operation of SDA is dependent on the status of

SYN pin. If SYN is high SDA is the output of serial bit data (read mode) if SYN is low

SDA is the input of serial bit data signal (write mode). If SCS is high SDA is idle.

When SCS is active (low), signal SDA should change its state at trailing edge of signal

SCL and the signal SDA should be stable at next leading edge of signal SCL. The first

valid bit of SDA is always started with activation of signal SCL.

2.1

Connection to microcontroller

The SPI master should be implemented by a host system, a PC or a microcontroller.

Microcontrollers SPI bus is usually a four wire bus with full duplex functionality, which signals

are usually named as:

●

SCLK: Serial Clock (output from master)

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MOSI: Master Output, Slave Input (output from master)

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MISO: Master Input, Slave Output (output from slave)

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SS: Slave Select (active low; output from master)