AN1978 - APPLICATION NOTE

4/14

Figure 4: Clock duty cycle on CLKDIV change

The clock signal can be obtained by a crystal connected between the XTAL1 and XTAL2 pins or by an

external signal applied to the XTAL1 pin; in this case the XTAL2 pin must be left floating. The external

signal voltage value must be enclosed between GND and VDD.

In the PCB design, in order to reduce the reflections especially for the high frequency, the Xtal should be

connected as close as possible to the XTAL pins, as shown in figure 5.

Figure 5: XTAL connection

Two compensation capacitors, lower than 22pF, can be used to improve the oscillator performance even

if the characterization tests remarked that the CLK Duty Cycle is enclosed between 45% and 55%,

CH1: output CLK waveform.

CH2: CLKDIV1 pin.

Conditions:

VDD=3.3V;

VDDP=5V;

5/3V=H;

CMDVCC=L.

F

CLKDIV2=0V;

The output Duty Cycle is 50%±5%

even if the Clock Division changes.

CH1: output CLK waveform.

CH2: CLKDIV1 pin.

Conditions:

VDD=3.3V;

VDDP=5V;

5/3V=H;

CMDVCC=L.

F

CLKDIV2=0V;

The output Duty Cycle is 50%±5%

even if the Clock Division changes.

XTAL1

VDD

XTAL2

GND

Compensation capacitors

2MHz to 26MHz XTAL (Y1)

100 mils