AN2785 datasheet(49/51 Pages) STMICROELECTRONICS

49 / 51 page

AN2785

Layout suggestions

Doc ID 14785 Rev 1

49/51

The group of LP1, LP2 and LP3 parasitic inductances is located along the low-side path of

each half-bridge, between the OUT pin and the GND of the related driver, and provides an

undesired contribution to the issue of below-ground voltage spikes on each OUT pin of the

L6393 (described in Section 9.1). In fact, at the beginning of the current recirculation on the

low-side switches, the current may experience a high dI/dt which is able to produce, on

those parasitic inductances, significant voltage spikes. Those spikes add up with the voltage

drop of the low-side diode and of the RSENSE (when present) and have a negative sign, so

the overall voltage drop between OUT and GND may be significant. The suggestion is to

limit as much as possible each contribution to this phenomenon by limiting the length of

tracks LP1, LP2 and LP3 and by using an RSENSE resistor with low intrinsic inductance. LP1

may be reduced by connecting the OUT line directly to the collector (or drain) of the low-side

IGBT (or MOSFET), LP2 may be reduced by placing the RSENSE resistor as close as

possible to the emitter (or source) of the low-side IGBT (or MOSFET). The LP3 may be

minimized by connecting the GND line (also called driver ground) of the related gate driver

directly to the RSENSE resistor.

LP4 represents the parasitic inductance located between the ground connections of each

gate driver (driver ground) and the ground connection of the application controller (also

called signal ground). Due to its location, this parasitic inductance introduces noise which is

experienced by the input logic signals and by the L6393 comparator output signal. In fact,

each phase of the bridge causes high currents (with high dI/dt) to flow on these paths,

causing voltage noise which drops between the gate driver ground and the controller

ground. This noise between the two grounds is directly added to all logic and analog voltage

signals between the gate driver and the micro-controller, including the input logic signals

and the analog output of the related comparator. It is recommended to minimize this noise

by reducing as much as possible the distance between the signal ground and the driver

ground (for each gate driver in the system). In general, it is recommended to connect the

signal ground to the various driver grounds through a star connection, in order to improve

the balancing and symmetry for any kind of driving topology.

Note:

Ground loops must be avoided; only a single path must connect two different ground nodes.

The LP5 parasitic inductance is not usually critical because it stands between the minus

terminal of the bulk capacitor and the signal/power ground: the spikes on this parasitic

element have little influence on other system nodes.

Another useful suggestion is to respect some distance between the lines that switch with

high-voltage transitions and the signal lines sensitive to electrical noise. The tracks of each

OUT phase bringing significant currents and high voltages should be separated from the

logic lines and analog sensing circuits of the comparators.

AN2785 Datasheet(PDF) 49 Page - STMicroelectronics