AN2847

Interrupt generation

Doc ID 15136 Rev 2

21/31

5.2

Threshold

Threshold registers define the reference accelerations used by the interrupt generation

circuitry. The value of 1LSB of these 7-bit registers depends on the selected full scale

(

Table 18).

5.3

Free-fall and wake-up interrupts

The LIS331DLH interrupt signals can behave as free-fall, wake-up or 6D orientation

detection. When an interrupt condition is verified, the interrupt signal is generated and by

reading the INT1_SRC and INT2_SRC registers it is possible to determine which condition

has occurred.

The Free-Fall signal (FF) and Wake-Up signal (WU) interrupt generation block is

represented in

Figure 8.

FF or WU interrupt generation is selected through the AOI bit in INTx_CFG register. If the

AOI bit is ‘0’, signals coming from comparators are put in logical “OR”. Depending on the

values written in the INT1_CFG register, every time the value of at least one of the enabled

axes exceeds the threshold written in module in INTx_THS registers, a WU interrupt is

generated. Otherwise, if the AOI bit is ‘1’, signals coming from the comparators go into a

“NAND” port. In this case, an interrupt signal is generated only if all the enabled axes

exceed the threshold written in the INTx_THS register.

The LIRx bits of the CTRL_REG3 can be used to determine whether or not the interrupt

request must be latched. If the LIRx bit is ‘0’ (default value), the interrupt signal goes high

when the interrupt condition is satisfied and immediately returns low if the interrupt condition

is no longer verified. Otherwise, if the LIRx bit is ‘1’, when an interrupt condition is applied,

the interrupt signal remains high even if the condition returns to a non-interrupt status, until

a reading of the INTx_SRC register is performed.

Table 17.

Duration LSB value in low power mode

ODR (Hz)

Duration LSB value (s)

0.5

2

11

20.5

50.2

10

0.1

Table 18.

Threshold LSB value

Full scale

Threshold LSB value (mg)

2~16

4~31

8~63