AN4163 datasheet(5/33 Pages) STMICROELECTRONICS

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AN4163

Main characteristics and circuit description

The main characteristics of the SMPS are listed below:



Input mains range: 90 to 265 Vac



Minimum line frequency (fL): 47 Hz



Regulated output voltage: 400 V



Rated output power: 350 W



Maximum 2fL output voltage ripple: 12.5 V (peak- to-peak)



Hold-up time: 20 ms (VDROP after hold-up time: 300 V)



Switching frequency: 70 kHz



Minimum efficiency: 94% (at Vin = 90 Vac, Pout = 350 W)



PCB: single-sided, 70 µm, CEM-1, 112 x 114 mm

The power stage of the PFC is a traditional boost PFC converter, connected to the output of

the rectifier bridge D2. It is comprised of the boost inductor L3, the power switch, formed by

the parallel of MOSFETs Q1 and Q2, the diode D3 and the output capacitors C3 and C4.

The 300 V varistor RV1, connected between the line and the neutral, protects the circuit

against high input voltage transients while the fuse F1 disconnects the mains in case of

short-circuit.

To meet the EMC standards, the board is equipped with an input EMI filter cutting the

switching noise coming from the boost stage. In particular L2 filters the common-mode

emissions while L1, C1, C2 reduce the differential-mode emissions.

The L4984D has to be supplied by an external power supply, connected between pin #1

(VCC) and pin #2 (GND) of J3.

The capacitor C14 connected to the TIMER (#7) pin determines the switching frequency.

The resistor divider R12, R16, R22 and R24 provides to the L4984D multiplier (MULT, pin

#3) the information of the instantaneous mains voltage that is used to modulate the peak

current of the boost, the TOFF duration and is fed to the VFF block.

The resistors R6, R8, R13 with R17 and R18 are dedicated to sense the output voltage and

feed to the inverting input of the error amplifier (INV, pin #1) the feedback information

necessary to keep the output voltage regulated. Between the INV (#1) and COMP (#2) pins,

the components C8, R21 and C11 form the error amplifier compensation network in order to

keep the required loop stability.

The inductor peak current is sensed by resistors R27, R30, R31 placed in series to the

MOSFETs’ source and the derived signal is fed into the current sense pin (CS, #4) of the

L4984D via the filter by R29 and C13. C15 and R28, connected to the VFF pin (#5),

complete an internal peak-holding circuit providing the information on the RMS mains

voltage, deriving a DC voltage equal to the peak of the MULT pin (#3) voltage, which is fed

to the multiplier to compensate the control loop gain dependence on the mains voltage.

The brownout function is also implemented using the VFF pin. A voltage below 0.8 V on the

VFF pin (#5) shuts down (no latch) the IC and brings its consumption to a considerably

lower level. The L4984D starts as the voltage at the pin rises above 0.88 V.

The divider R5, R10, R14 and R23 provides to the L4984D PFC_OK pin (#7) the information

of the output voltage level, to trigger the dynamic OVP protection, preventing the output

voltage from excessive values during the load transients due to the slow response caused

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