AN4504 datasheet(31/41 Pages) STMICROELECTRONICS

31 / 41 page

DocID026419 Rev 1

31/41

AN4504

First-in first-out (FIFO) buffer

6.3

FIFO modes

The L3G4200D FIFO buffer can be configured to operate in five different modes selectable

by the FM[2:0] field in FIFO_CTRL_REG. Available configurations ensure a high level of

flexibility and extend the number of functions usable in application development.

Bypass, FIFO, Stream, Stream-to-FIFO and Bypass-to-Stream modes are described in the

following paragraphs.

6.3.1

Bypass mode

When Bypass mode is enabled, FIFO is not operational: buffer content is cleared, output

registers (0x28 to 0x2D) are frozen at the last value loaded, and the FIFO buffer remains

empty until another mode is selected.

Follow these steps for Bypass mode configuration:

Turn-on FIFO by setting the FIFO_EN bit to “1” in control register 5 (0x24). After this

operation the FIFO buffer is enabled but isn’t collecting data, output registers are

frozen to the last samples set loaded.

Activate Bypass mode by setting the FM[2:0] field to “000” in the FIFO control register

(0x2E). If this mode is enabled, the FIFO source register (0x2F) is forced equal to 0x20.

Bypass mode must be used in order to stop and reset the FIFO buffer when a different

mode is operating. Note that placing the FIFO buffer into bypass mode clears the whole

buffer content.

6.3.2

FIFO mode

In FIFO mode, the buffer continues filling until full (32 sample sets stored,) then it stops

collecting data and the FIFO content remains unchanged until a different mode is selected.

Follow these steps for FIFO mode configuration:

Turn on FIFO by setting the FIFO_EN bit to “1” in control register 5 (0x24). After this

operation the FIFO buffer is enabled but isn’t collecting data, output registers are

frozen to the last sample set loaded.

Activate FIFO mode by setting the FM[2:0] field to “001” in the FIFO control register

(0x2E).

By selecting this mode, FIFO starts data collection and source register (0x2F) changes

according to the number of samples stored. At the end of the procedure, the source register

is set to 0xDF and the OVRN flag generates an interrupt if the I2_OVRN bit is selected in

control register 5. Data can be retrieved when OVRN is set to ‘1’, performing a 32 sample

set read from the output registers, data can be retrieved also on the WTM flag instead of

OVRN if the application requires a lower number of samples. Communication speed is not

so important in FIFO mode because data collection is stopped and there is no risk of

overwriting acquired data. Before restarting FIFO mode, at the end of the reading procedure

it is necessary to exit Bypass mode.

AN4504 Datasheet(PDF) 31 Page - STMicroelectronics

AN4504 Datasheet(HTML) 31 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Download

Link URL