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UPD6345GS Datasheet(PDF) 3 Page - NEC |
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UPD6345GS Datasheet(HTML) 3 Page - NEC |
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3 / 16 page  3 µPD6345 TRUTH TABLE SCK EN RES LAT SIN OUT SO*1 Note O1 On H H H L High Impedance On – 1 S7 HHHH L On – 1 S7 HH L*2 * NO CHANGE NO CHANGE S7 L H * * High Impedance High Impedance S7 **** NO CHANGE NO CHANGE S8 * * L H * High Impedance High Impedance L * H L * NO CHANGE NO CHANGE L *1) Seventh data S7 of shift register is loaded to eighth data S8 on positive-going transition of clock, and is output to Serial data Output pin. *2) Shift register operates normally. BLOCK DIAGRAM O1 O2 O3 O4 O5 O6 O7 O8 P1 P2 P3 P4 P5 P6 P7 P8 S1 S2 S3 S4 S5 S6 S7 S8 SO EN LAT SIN RES SCK 100 k Ω 100 k Ω 100 k Ω 100 k Ω 100 k Ω P1 to P8 ; Latch Circuits S1 to S8 ; 8-bit Shift register SCK = CLOCK EN = Output Enable RES= Reset LAT= Latch Enable SIN = Serial data Input OUT = Driver Output SO = Serial data Output * = H or L H = High level L = Low level |
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