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AN3427 Datasheet(PDF) 13 Page - STMicroelectronics |
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AN3427 Datasheet(HTML) 13 Page - STMicroelectronics |
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13 / 52 page ![]() AN3427 Peripheral migration Doc ID 019001 Rev 1 13/52 3.2.3 Dual SRAM The 128KB of SRAM is made of 2 blocks; one 112KB and one 16KB. Both can be accessed simultaneously by 2 masters in 0 WS (CPU, DMAs, Ethernet, USB HS). The 16KB SRAM can be used as a buffer for high speed peripherals like USB-HS, Ethernet, Camera, without impacting the CPU performance. 3.3 Memory mapping The peripheral address mapping has been changed in the F2 series vs. F1 series, the main change concerns the GPIOs which have been moved to the AHB bus instead of the APB bus to allow them to operate at maximum speed. The tables below provide the peripheral address mapping correspondence between F2 and F1 series. Table 3. IP bus mapping differences between STM32 F1 and STM32 F2 series Peripheral STM32 F2 series STM32 F1 series Bus Base address Bus Base address FSMC Registers AHB3 0xA0000000 AHB 0xA0000000 RNG AHB2 0x50060800 NA NA HASH 0x50060400 NA NA CRYP 0x50060000 NA NA DCMI 0x50050000 NA NA USB OTG FS 0x50000000 AHB 0x50000000 |
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