PM0056 datasheet(16/156 Pages) STMICROELECTRONICS

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The Cortex-M3 processor

PM0056

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DocID15491 Rev 5

Program status register

The Program Status Register (PSR) combines:

•

Application Program Status Register (APSR)

•

Interrupt Program Status Register (IPSR)

•

Execution Program Status Register (EPSR)

These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are

as shown in Figure 3 and Figure 4.

Figure 3. APSR, IPSR and EPSR bit assignments

Figure 4. PSR bit assignments

Access these registers individually or as a combination of any two or all three registers,

using the register name as an argument to the MSR or MRS instructions. For example:

•

Read all of the registers using PSR with the MRS instruction

•

Write to the APSR using APSR with the MSR instruction.

The PSR combinations and attributes are:

See the instruction descriptions MRS on page 100 and MSR on page 101 for more

information about how to access the program status registers.

Table 3. PSR register combinations

Type

Combination

PSR

read-write(1), (2)

1. The processor ignores writes to the IPSR bits.

2. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits

APSR, EPSR, and IPSR

IEPSR

read-only

EPSR and IPSR

IAPSR

read-write(1)

APSR and IPSR

EAPSR

read-write(2)

APSR and EPSR

25 24 23

Reserved

ISR_NUMBER

31 30 29 28 27

NZC V

Reserved

APSR

IPSR

EPSR

Reserved

16 15

10 9

Reserved

ICI/IT

31 30 29 28 27 26 25 24 23

16 15

10 9 8

Z C V Q ICI/IT T

Reserved

ICI/IT

ISR_NUMBER

Reserved

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