UM0097 datasheet(31/229 Pages) STMICROELECTRONICS

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UM0097

Peripheral firmware overview

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Table 11 lists the different values of the clock divider parameter.

RCLK clock source

The following enumeration defines the RCLK clock sources. RCLK_Clocks enumeration is

defined in the file 71x_rccu.h:

typedef enum

{

RCCU_PLL1_Output,

RCCU_CLOCK2_16,

RCCU_CLOCK2,

RCCU_CK_AF

} RCCU_RCLK_Clocks;

Table 12 describes the RCLK clock sources.

PLL1 multiplication factors

The following enumeration defines the PLL1 multiplication factors. RCCU_PLL1_Mul

enumeration is declared in the file 71x_rccu.h:

typedef enum

{

RCCU_PLL1_Mul_12 = 0x01,

RCCU_PLL1_Mul_16 = 0x03,

RCCU_PLL1_Mul_20 = 0x00,

RCCU_PLL1_Mul_24 = 0x02

} RCCU_PLL1_Mul;

Table 11.

Clock divider parameters

Clock Divider

Description

RCCU_DEFAULT

The default divider (reset value) division by 1

RCCU_RCLK_2

Divide the RCLK by 2

RCCU_RCLK_4

Divide the RCLK by 4

RCCU_RCLK_8

Divide the RCLK by 8

Table 12.

RCLK clock sources

RCLK Clock Source

Description

RCCU_PLL1_Output

Select the PLL1 output as RCLK clock source

RCCU_CLOCK2_16

Select the RCLK2/16 as RCLK clock source

RCCU_CLOCK2

Select the Clock2 as RCLK clock source

RCCU_CK_AF

Select the RTC as RCLK clock source

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